FAQs
- All FAQ Articles
- 5.0V Clock required - Use 3.3V CMOS Clock
- Ceramic Packaged Oscillators with "S" in the PN
- Converting Clipped Sinewave Output to CMOS
- Deterministic Jitter
- Fine Leak Testing Criteria
- Frequency Stability - No 100ppm specifications?
- LVDS driving mutliple inputs
- Part Numbering and Marking
- Phase Noise to Jitter Conversion
- Pletronics Inc. -- Sales Terms and Conditions
- Shock level and broken crystals causing failures
- Suggesting PCB/PWB pad geometries
- Symmetry - Why only 45/55%?
- The advantages of using LVDS
- Total Jitter
- Why do TCXOs have clipped sinewave outputs?
- Why does a crystal have a lower frequency limit?